Simplified diagram showing a pair of CAN busses being used to support low and high speed devices.
CAN uses a bi-directional control system designed to operate using three wires: two signal wires, the CANH and CANL wires, and a common ground. If the cable is shielded, the shield is only grounded at one end of the bus. In some applications, a fourth voltage supply wire can be added, for example including a 12V power bus.
The CANH, CANL, and Ground wires are connected to all CAN nodes. They are polarity sensitive so CANH must be connected to CANH and CANL to CANL.
While it would be usual to wire the bus sequentially round the various modules, this is not essential. Individual nodes can be star connected if this is more convenient.
Like other serial bus designs, a CAN bus requires termination resistors. If the bus is wired sequentially round the modules, then a resistor of 120 ohms should be fitted across the bus at each end. (Smaller buses (or short length) might use just one 60 Ohm resistor between the CANH and CANL wires.)
Simplified diagram showing a pair of CAN busses being used to support low and high speed devices.
The CAN protocol uses Non-Return-to-Zero or NRZ bit coding. This means that the signal is constant for one whole bit time and only one time segment is needed to represent one bit. The two bus conductors are driven differentially in balanced mode. The signal levels are shifted, resulting in a waveform that differs to that of EIA-485.
The maximum CAN bus speed is 1 MBaud, which can be achieved with a bus length of up to 40 meters when using a twisted wire pair. For bus lengths longer than 40 meters the bus speed must be reduced. A 1000 meter bus can still be realised with a 50 KBaud bus speed. For a bus length above 1000 meters, a design needs to use specific speed line drivers .
CAN Physical Interface.
The shifted level results in an unusual voltage signalling method that is designed to allow bus arbitration. Each bit is are a dominant bit, low/0, or a recessive bit, high/1. As the name suggests dominate bits take precedence on the bus, over recessive bits when both are sent at the same time by different nodes.
In more detail, CAN singalling represents a 1 and 0 in the following way using 3 signal levels:
This design results in a constant power envelope. That is, the power does not vary depending on the information content.
Sequence for 1 followed by 0:
Example waveform showing transmission of the sequence { 0 0 1 1 0 1 }. Vertical axis in volts, horizontal axis in microseconds.
Synchronous transmission is used. That is the sender transmits all bits at the same clock rate. There are no start or stop bauds inserted.
Bit stuffing is used. This stuffing avoids a sender transmitting for excessive period at the same level. This is designed to ensure receiving nodes are able to maintain their clock synchronisation.
When transmitting uisng Bit Stuffing, the sender observes the sequence of bit values being sent. A maximum of five consecutive bits are allowed to have the same polarity. Whenever five consecutive bits of the same polarity have been transmitted, the transmitter will itself adds one bit of the opposite polarity to the previous 5 bits. This is inserted into the bit stream before transmitting further bits. This method can add up to one bit in five, introducing a maximum of 20% additional overhead.
The receiver checks the number of bits received with the same polarity. It removes one bit (the stuff bit) when it sees the previous 5 bits hav the same value. This is called destuffing, and restores the original bit sequence.
Examples of Bit Stuffing:
For example, the sequence 0111111 becomes 01111101 on the wire, but the receiver correctly receives 0111111. Bit stuffing dictates also that the 0111110 becomes 01111100 on the wire, but the receiver then destuff this and receives 0111110, i.e., the receiver will automatically remove any bit after 5 consecutive identical bits.
More examples using Bit Stuffing: a sequence 0111111 becomes 01111101 on the wire, but the receiver correctly receives 0111111 after removing the extra "stuffed" bit.
1010101001 sent on cable, received as 1010101001In correct reception, the removed stuffing bit must always be the opposite polarity to the preceding 5 bits. If the destuffed bit is not of the opposite polarity, then the frame is considered corrupted and is counted as a frame error.
There is am advantage of being able to send any binary data, while preserving clock transitions. However, this has a disadavantage also. in that any errors can result in insertion or deletion of bits. While this is likely to be uncommon in practice (there are not usually many stuffing bits - so it is unlikely that they will be corrupted), the receiver must use an integrity that provides a strong guarantee of detecting destuffing mistakes. A Cyclic Redundancy Check is usually used.
Examples of problems thatcan arise when any stuffed stream is corrupted (i.e. a bit is inverted):
A CAN node does not immediately know if the data it sends will be received (arbitration can over-ride one message with a higher priority message). Therefore, CAN introduces the acknowledge (ACK) field at the end of each frame. This is sent with a single recessive bit followed by a dominate followed by another recessive bit (marking the End of Frame (EoF). The ACK field is important to show that at least one receiving node on the bus has seen the frame sent by a transmitter, which is done by setting the ACK field to dominant. Therefore a sending node reads the ACK field of its frame from the bus: a dominate bit indicates that transmission was successful, a recessive indicates transmission was unsuccessful, resulting in sending an error frame (and possible retransmission).
An eror frames intentionally adds bit stuffing errors to clear the bus. This can either be active error frames or passive error frames. Active error frames contain 6 dominate bits, followed by 8 delimiter bits and 3 interframe bits. Passive error frames contain 6 recessive bits, 8 delimiter bits, and 3 inter-frame bits.
See also
Prof. Gorry Fairhurst, School of Engineering, University of Aberdeen, Scotland (2024)