- Pentium 4 Uniprocessor
- Pentium III dual CPU SMP
- Pentium Dual-Core Xeon SMP
- Pentium M laptop
- Sparc64 Ultra80
The comparisons were simple `before/after' tests.
3.1 Pentium 4
The following figure shows the impact of disabling the send-credit
patch on the i386 (data
before and
after):
3.2 Xeon 3Ghz dual core
The same trend was observed on the dual
core SMP box (
before and
after):
3.3 Sparc64 Ultra80
On the sparc64 the trend is less drastic than on the i386, but still
noticeable (
before and
after):
4. Experiments with different values of HZ
In addition to the above experiments (which were all run at HZ=1000), a
throughput comparison was performed with a Pentium M tickless system
(DYNTICKS) and a value of HZ=250, since this challenges the accuracy of
the scheduling. The results were:
- 2.6.22 netdev as of 20/7: 84.6
Mbits/sec
- DCCP test tree as of
20/7: 4.33
Mbits/sec
- DCCP test tree
patched: 92.8 Mbits/sec
5. rfc3448bis suggestions
The current wisdom in
rfc3448bis
is to allow accumulation of send credits of up to one RTT. It was tried
to implement this `blindly', i.e. as the draft suggests. The
performance was as `bad' as with the send-credits patch (which limits
accumulation of up to 1 t_ipi instead of 1 RTT). It therefore seems
that it is a bad idea to use such throttling with the current
implementation of the DCCP packet scheduler.