Universal Asynchronous Receiver/Transmitters

Universal Asynchronous Receiver/Transmitters implement logic to transmit and receive asynchronous signals. These are commonly available as separate chips, but are often integrated in microcontrollers. At the typical baud rates used for asynchronous communication, they can also be implemented in software.

UARTs can be interfaced as an I/O controller to a computer bus and via a serial line driver to the physical layer cable.

An asynchronous link communicates data as a series of bytes of fixed size and format. Each byte is preceded by a start baud and followed by either 1 or 2 stop bauds. The asynchronous transmitter delimits each byte by a start sequence and a stop sequence. The start bit (0), data (usually 8 bits plus parity) and stop bit(s) (1) are transmitted using a shift register clocked at the nominal data rate.

An Asynchronous byte transmission (shows the unbalanced line or Data+ line of a balanced transmission line).

The setup of the UART is controlled by a set of configuration registers written via the PC bus. Examples of parameters include:

Many UARTs use a divider chain to divide the frequency of a clock signal to generate a set of baud rate clocks used at the sender and receiver. This clock signal (square wave signal) may be created using a crystal oscillator circuit. In most cases, the clock is derived from a small crystal oscillator. In general, whatever method is used, the clock will be of too high a frequency for the UART, the clock frequency may however be easily reduced using a succession of frequency dividers (each a flip-flop wired to divide the input clock by 2). In general, this does not allow arbitrary selection of the baud rate, but fortunately asynchronous framing does not require accurate clocks.

Asynchronous communications is often used to support text-based applications that use the ASCII character set, but can also be used to transmit any binary value.


A data byte is typically loaded in parallel from the transmit FIFO. Data is sent by supplying a transmit (tx) clock (from the transmit baud rate generator) to shift out the data serially, starting with the start bit.

Asynchronous transmission - each byte is framed by a start and one or more stop bits. The first bit on the wire is the start bit followed by the least significant data bit.


At the receiver, a receive (rx) clock of the same nominal frequency is constructed and used to clock-in the data to the receive shift register.

The receiver does not run continuously, instead it is started by detecting the edge (downwards transition) of the start baud. This triggers reception of the 11-bit slot/character using a shift register clocked by the locally generated receive clock at the same nominal baud rate used by the transmitter.

This is shown below:

The transition from the idle state triggers the UART at the receiver to start reception

The receive ((rx) clock is normally generated using a local stable high rate clock, frequently operating at least 2 times the intended data rate, as shown above this can be used, to find the size of a half-bit period, and align the timing with the mid position of the start bit. The number of bits to be converted is the number corresponding to one half the original bit period, 8 high frequency clock cycles in this example using a 16x baud rate reference). From there the centre of the successive bits are located by counting cycles corresponding to the original data speed (16 cycles per baud in this example).

After 11 clock cycles (assuming 2 stop bits, no parity), the contents of the shift register is checked. Only data that are bounded by the correct start and stop bits are accepted, i.e. where the stop bit is one (or the two bits are both 1). Valid bytes are passed to the receive FIFO for processing by the protocol's link layer.

There are several errors that may result in corruption - e.g. transmitter overrun, receiver underrun, bit errors, timing errors, and signal breaks.

The break sequence may be used by the receiver to detect when the cable breaks, or in the case of DMX 512, to detect the start of a frame.

Transmit and Receive Baud Rate

A receiver uses a clock pre-configured to the same nominal baud rate as set by the transmitter. Ideally this allows it to sample the signal in the centre of each baud-period. However, it is hard for two clocks in different places to remain synchronised perfectly. Small differences in design, temperature, etc can lead to drift of one relative to another.

If the receiver baud rate is different to the sender, the clocks will slip in time (phase) relative to one another, the more bits since the start of the byte, the bigger the slip, until finally one bit will not be sampled (or will be sampled at the edge of the waveform, where the signal is weaker.) If observed over a sufficiently long period will result in a receive error.

Consider a link operating at 9600 baud.

B= 1 baud = 1/9600 = 1.04 mS 1 slot = 11 baud (assuming two stop bauds).

A sender at this baud rate starts the last (msb) data bit of the slot at 8*B S after the start bit, i.e. at 8.32 mS. The msb bit is completed at 9*B S after the start bit, i.e. at 9.36 mS

A receiver with a baud rate also set to 9600 bps, samples the last baud at a time 8.5 *B ┬ÁS after the start baud has been seen = 8.84 mS. This results in the received baud being sampled at the centre of the baud period, exactly as we would have hoped.

Now consider what would happen if the transmit baud clock was just 2% different in frequency to the receiver baud clock. The 2% lower sender rate results in the last baud of a slot starting at 8*B*.98 and ending at t 9*B*.98. We already know that the receiver will sample the baud at 8.84 mS, so this results in sampling just at the end of the last baud period, rather than at the centre of the baud, in theory this could be OK (i.e. the bauds would be correctly received), but it could increase the probability of a bit error if there was a degraded signal, since practical line drivers limit the slew rate and the receiver is not sampling at the centre of the baud. In general, a receiver will work with a receiver baud rate that is 2% or less different to the sender baud rate.

However, a larger difference will clearly not work. A 10% difference would result in the receiver failing to sample the final baud - resulting in corruption of the data (it would sample after the last baud has been received).

First-In-First-Out (FIFO) Buffers

A transmitter (Tx) FIFO required to prevent under-run. The TX FIFO allows the microcontroller to store values that will be sent by the UART over the serial bus. A typical arrangement uses a FIFO of depth 2, this relaxes timing requirements for the microcontroller while still allowing it to send continuously (double buffering). A status flag is used to signal that there is space for more data. If the sender fails to send fast enough, a transmit under-run simply results in idle time between asynchronous slots.

The RX FIFO prevents receiver over-run when the microcontroller can not service the UART promptly. Since overruns result in loss of data this is usually seen as much more important than avoiding underrun of the Tx, and a larger FIFO is common (e.g. depth 4, which is common). A deeper receiver FIFO is often needed to avoid overrun of the receiver. This is more critical in that data can arrive from the bus would be missed if not buffered.

Most UARTs set a status overrun flag in their status register to inform the connected computer that data has been lost.

Flags in the statis regsier also typically indicate when characters do not have a valid stop baud(s) and when a break signal is seen on the receive line.

See also:

Prof. Gorry Fairhurst, School of Engineering, University of Aberdeen, Scotland. (2018)